Silicon Laboratories C8051F347 - Manual (Page 100)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
100 Rev. 1.3
11. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For V
DD
Monitor and Power-On Resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to
Section “14. Oscillators” on page 131 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (
Section “22.3. Watchdog Timer Mode” on page 264 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
Figure 11.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot)
Software Reset (SWRSF)
System Reset
Reset
Funnel
Px.x
Px.x
EN
System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
Clock Select
EN
WD
T
Ena
b
le
MCD
Ena
b
le
Errant
FLASH
Operation
+
-
Comparator 0
C0RSEF
RST
(wired-OR)
Power On
Reset
+
-
VDD
Supply
Monitor
Enable
'0'
Internal HF
Oscillator
XTAL1
XTAL2
External
Oscillator
Drive
Clock
Multiplier
USB
Controller
VBUS
Transition
Ena
b
le
Internal LF
Oscillator