Silicon Laboratories C8051F347 - Manual (Page 102)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
102 Rev. 1.3
11.2. Power-Fail Reset / V
DD
Monitor
When a power-down transition or power irregularity causes V
DD
to drop below V
RST
, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When V
DD
returns
to a level above V
RST
, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if V
DD
dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
DD
monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any
other reset source. For example, if the V
DD
monitor is enabled and a software reset is performed, the V
DD
monitor will still be enabled after the reset. It is strongly recommended that the V
DD
monitor be left enabled
at all times for any system that contains code to write to Flash memory.
Important Note: The V
DD
monitor must be enabled before it is selected as a reset source. Selecting the
V
DD
monitor as a reset source before it is enabled and stabilized may cause a system reset. In applica-
tions where this reset is undesirable, a delay can be implemented between enabling the V
DD
monitor and
selecting it as a reset source. The procedure for configuring the V
DD
monitor as a reset source is shown
below:
Step 1. Enable the V
DD
monitor (VDM0CN.7 = ‘1’).
Step 2. If desired, wait for the V
DD
monitor to stabilize (see Table 11.1 for the V
DD
Monitor turn-on
time).
Step 3. Select the V
DD
monitor as a reset source (RSTSRC.1 = ‘1’).
See Figure 11.2 for V
DD
monitor timing. See Table 11.1 for complete electrical characteristics of the V
DD
monitor.
SFR Definition 11.1. VDM0CN: V
DD
Monitor Control
Bit7: VDMEN: V
DD
Monitor Enable.
This bit turns the V
DD
monitor circuit on/off. The V
DD
Monitor cannot generate system resets
until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2). The V
DD
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
DD
monitor as a reset source before it has stabilized will generate a system reset.
See Table 11.1 for the minimum V
DD
Monitor turn-on time. The V
DD
Monitor is enabled fol-
lowing all POR resets.
0: V
DD
Monitor Disabled.
1: V
DD
Monitor Enabled.
Bit6: V
DD
STAT: V
DD
Status.
This bit indicates the current power supply status (V
DD
Monitor output).
0: V
DD
is at or below the V
DD
monitor threshold.
1: V
DD
is above the V
DD
monitor threshold.
Bits5–0: Reserved. Read = Variable. Write = don’t care.
R/W R R R R R R R Reset Value
VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xFF