Silicon Laboratories C8051F347 - Manual (Page 104)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
104 Rev. 1.3
11.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
11.9. USB Reset
Writing ‘1’ to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must
be enabled for RESET signaling to be detected. See
Section “16. Universal Serial Bus Con-
troller (USB0)” on page 159 for information on the USB Function Controller.
2. The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register
REG0CN. See
Section “8. Voltage Regulator (REG0)” on page 69 for details on the VBUS
detection circuit.
The USBRSF bit will read ‘1’ following a USB reset. The state of the RST pin is unaffected by this reset.