Silicon Laboratories C8051F347 - Manual (Page 125)

Rev. 1.3 125
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’.
Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing
EMIF ADDRESS (8 LSBs) from R0 or R1 P3
P2
P1.7
P1.6
P4 EMIF WRITE DATA
P3
P1.7
P1.6
P4
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WR
RD
EMIF ADDRESS (8 LSBs) from R0 or R1 P3
P2
P1.6
P1.7
P4
P3
P1.6
P1.7
P4
T
ACH
T
RDH
T
ACW
T
ACS
T
RDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
RD
WR
EMIF READ DATA
Nonmuxed 8-bit WRITE without Bank Select
Nonmuxed 8-bit READ without Bank Select