Silicon Laboratories C8051F347 - Manual (Page 129)

Rev. 1.3 129
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’.
Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.7
P1.6
P1.3
P1.7
P1.6
P1.3
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.6
P1.7
P1.3
P1.6
P1.7
P1.3
T
ACH
T
ACW
T
ACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL T
RDH
T
RDS
EMIF READ DATA
Muxed 8-bit WRITE with Bank Select
Muxed 8-bit READ with Bank Select