Silicon Laboratories C8051F347 - Manual (Page 130)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
130 Rev. 1.3
Table 13.1. AC Parameters for External Memory Interface
Parameter Description Min* Max* Units
T
ACS
Address / Control Setup Time 0 3 x T
SYSCLK
ns
T
ACW
Address / Control Pulse Width 1 x T
SYSCLK
16 x T
SYSCLK
ns
T
ACH
Address / Control Hold Time 0 3 x T
SYSCLK
ns
T
ALEH
Address Latch Enable High Time 1 x T
SYSCLK
4 x T
SYSCLK
ns
T
ALEL
Address Latch Enable Low Time 1 x T
SYSCLK
4 x T
SYSCLK
ns
T
WDS
Write Data Setup Time 1 x T
SYSCLK
19 x T
SYSCLK
ns
T
WDH
Write Data Hold Time 0 3 x T
SYSCLK
ns
T
RDS
Read Data Setup Time 20 ns
T
RDH
Read Data Hold Time 0 ns
*Note: T
SYSCLK
is equal to one period of the device system clock (SYSCLK).