No pins skipped), Nd figure 15.4). th – Silicon Laboratories C8051F347 User Manual
Page 145
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Rev. 1.3
145
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 15.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped)
XT
A
L
1
XT
A
L
2
CNV
S
T
R
VR
EF
XT
A
L
1
XT
A
L
2
AL
E
CN
V
S
T
R
VR
EF
RD
WR
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
MISO
MOSI
NSS*
*NSS is only pinned out in 4-wire SPI mode
CP0
CP0A
CP1
T1
TX1**
**UART1 available only on C8051F340/1/4/5/8/A/B devices
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Example:
XBR0 = 0x07
XBR1 = 0x43
P3
P3SKIP[0:7]
SF Signals
(48-pin
Package)
P3.1-P3.7 unavailable on
the 32-pin packages
P2
CEX3
CEX4
P1SKIP[0:7]
P1
CP1A
CEX2
CEX0
CEX1
SYSCLK
RX0
SDA
SCL
P0
SF Signals
(32-pin
Package)
PIN I/O
TX0
ECI
T0
RX1**
P2SKIP[0:7]
Special Function Signals are not assigned by the Crossbar. When these signals are
SF Signals
P0SKIP[0:7]
Port pin assigned to peripheral by the Crossbar
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