Silicon Laboratories C8051F347 - Manual (Page 186)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
186 Rev. 1.3
USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte
USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low
USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High
Bit7: DBOEN: Double-buffer Enable
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
Bit6: ISO: Isochronous Transfer Enable
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
Bits5–0: Unused. Read = 000000b; Write = don’t care.
R/W R/W R/W R/W R R R R Reset Value
DBOEN ISO - - - - - - 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:
0x15
Bits7–0: EOCL: OUT Endpoint Count Low Byte
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
R R R R R R R R Reset Value
EOCL 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:
0x16
Bits7–2: Unused. Read = 00000. Write = don’t care.
Bits1–0: EOCH: OUT Endpoint Count High Byte
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
R R R R R R R R Reset Value
- - - - - - E0CH 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:
0x17