Silicon Laboratories C8051F347 - Manual (Page 212)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
212 Rev. 1.3
Table 18.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator
Target
Baud
Rate (bps)
Actual
Baud
Rate (bps)
Baud
Rate Error
Oscillator
Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale
select*
T1M* Timer 1
Reload
Value (hex)
S
YSCLK =
12
MHz
230400 230769 0.16% 52 SYSCLK XX 1 0xE6
115200 115385 0.16% 104 SYSCLK XX 1 0xCC
57600 57692 0.16% 208 SYSCLK XX 1 0x98
28800 28846 0.16% 416 SYSCLK XX 1 0x30
14400 14423 0.16% 832 SYSCLK / 4 01 0 0x98
9600 9615 0.16% 1248 SYSCLK / 4 01 0 0x64
2400 2404 0.16% 4992 SYSCLK / 12 00 0 0x30
1200 1202 0.16% 9984 SYSCLK / 48 10 0 0x98
SYSCLK =
24
MHz
230400 230769 0.16% 104 SYSCLK XX 1 0xCC
115200 115385 0.16% 208 SYSCLK XX 1 0x98
57600 57692 0.16% 416 SYSCLK XX 1 0x30
28800 28846 0.16% 832 SYSCLK / 4 01 0 0x98
14400 14423 0.16% 1664 SYSCLK / 4 01 0 0x30
9600 9615 0.16% 2496 SYSCLK / 12 00 0 0x98
2400 2404 0.16% 9984 SYSCLK / 48 10 0 0x98
1200 1202 0.16% 19968 SYSCLK / 48 10 0 0x30
SYSCLK = 48
MHz
230400 230769 0.16% 208 SYSCLK XX 1 0x98
115200 115385 0.16% 416 SYSCLK XX 1 0x30
57600 57692 0.16% 832 SYSCLK / 4 01 0 0x98
28800 28846 0.16% 1664 SYSCLK / 4 01 0 0x30
14400 14388 0.08% 3336 SYSCLK / 12 00 0 0x75
9600 9615 0.16% 4992 SYSCLK / 12 00 0 0x30
2400 2404 0.16% 19968 SYSCLK / 48 10 0 0x30
X = Don’t care
*Note: SCA1-SCA0 and T1M define the Timer Clock Source. Bit definitions for these values can be found in
Section 21.1 .