Silicon Laboratories C8051F347 - Manual (Page 225)

Rev. 1.3 225
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 20.2. Multiple-Master Mode Connection Diagram
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram
Master
Device 2
Master
Device 1
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO NSS
GPIO
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device MOSI
MISO
SCK
NSS