Silicon Laboratories C8051F347 - Manual (Page 252)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
252 Rev. 1.3
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)
SYSCLK
TCLK
0
1
TR3
External Clock / 8
SYSCLK / 12 0
1
1
0
TMR3H
TMR3RLH
TCLK TMR3L
TMR3RLL
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3CN
T
F
3
H
T
F
3
L T
3
X
C
L
K
T
3
C
S
S
T
R
3
T
F
3
L
E
N
T
3
C
E
T
3
S
P
L
I
T
Capture
Enable Capture Interrupt
USB Start-of-Frame (SOF)
Low-Frequency Oscillator
Falling Edge
0
1
T3CSS