Sfr definition 7.3 and – Silicon Laboratories C8051F347 User Manual
Page 64
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
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Rev. 1.3
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5:
CP0RIE: Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 rising-edge interrupt disabled.
1: Comparator0 rising-edge interrupt enabled.
Bit4:
CP0FIE: Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 falling-edge interrupt disabled.
1: Comparator0 falling-edge interrupt enabled.
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
* See Table 7.1 for response time parameters.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
CP0RIE
CP0FIE
-
-
CP0MD1
CP0MD0 00000010
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x9D
Mode
CP0MD1
CP0MD0
CP0 Response Time*
0
0
0
Fastest Response
1
0
1
2
1
0
3
1
1
Lowest Power