Datasheet, Ddr3l sdram, Unbuffered dimm – Samsung M391B5773DH0 User Manual
Page 32: Rev. 1.0
- 32 -
datasheet
DDR3L SDRAM
Rev. 1.0
Unbuffered DIMM
[ Table 21 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Reset Timing
Exit Reset from CKE HIGH to a valid command
tXPR
max(5nCK,
tRFC +
10ns)
-
max(5nCK,
tRFC +
10ns)
-
max(5nCK,
tRFC +
10ns)
-
max(5nCK,
tRFC +
10ns)
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
tXS
max(5nCK,t
RFC +
10ns)
-
max(5nCK,t
RFC +
10ns)
-
max(5nCK,t
RFC +
10ns)
-
max(5nCK,t
RFC + 10ns)
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
nCK
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
tCKSRE
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
tCKSRX
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
tXP
max
(3nCK,
7.5ns)
-
max
(3nCK,
7.5ns)
-
max
(3nCK,6ns)
-
max
(3nCK,6ns)
-
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
tXPDLL
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
2
CKE minimum pulse width
tCKE
max
(3nCK,
7.5ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,5ns)
-
Command pass disable delay
tCPDED
1
-
1
-
1
-
1
-
nCK
Power Down Entry to Exit Timing
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCK
15
Timing of ACT command to Power Down entry
tACTPDEN
1
-
1
-
1
-
1
-
nCK
20
Timing of PRE command to Power Down entry
tPRPDEN
1
-
1
-
1
-
1
-
nCK
20
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
nCK
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
WL + 4
+WR +1
-
WL + 4
+WR +1
-
WL + 4
+WR +1
-
WL + 4 +WR
+1
-
nCK
10
Timing of WR command to Power Down entry
(BC4MRS)
tWRPDEN
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
nCK
9
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDEN
WL +2 +WR
+1
-
WL +2 +WR
+1
-
WL +2 +WR
+1
-
WL +2 +WR
+1
-
nCK
10
Timing of REF command to Power Down entry
tREFPDEN
1
-
1
-
1
-
1
-
20,21
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
ODT Timing
ODT high time without write command or with write
command and BC4
ODTH4
4
-
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
6
-
nCK
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
2
8.5
ns
RTT turn-on
tAON
-400
400
-300
300
-250
250
-225
225
ps
7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
8,f
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
f
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
40
-
40
-
40
-
40
-
tCK
3
DQS/DQS delay after tDQS margining mode is pro-
grammed
tWLDQSEN
25
-
25
-
25
-
25
-
tCK
3
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS crossing
tWLH
325
-
245
-
195
-
165
-
ps
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
325
-
245
-
195
-
165
-
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
0
7.5
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
0
2
ns