Silicon Laboratories SI4421 - Manual (Page 2)

Si4421
2
DETAILED FEATURE-LEVEL DESCRIPTION
The Si4421 FSK transceiver is designed to cover the unlicensed
frequency bands at 433, 868 and 915 MHz. The device
facilitates compliance with FCC and ETSI requirements.
The receiver block employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The Si4421 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna
tuning, an LNA with switchable gain, I/Q down converter mixers,
baseband filters and amplifiers, and an I/Q demodulator
followed by a data filter.
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip crystal-
controlled reference oscillator. The PLL’s high resolution allows the
usage of multiple channels in any of the bands.
RF Power Amplifier (PA)
The power amplifier has an open-collector differential output and
can directly drive different PCB antennas with a programmable
output power level. An automatic antenna tuning circuit is built in
to avoid costly trimming procedures and the so-called “hand
effect”.
LNA
The LNA has approximately 250 Ohm input impedance, which
functions well with the proposed antennas (see: Application
Notes available from www.silabs.com/integration)
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct
matching and to minimize the noise figure of the receiver.
The LNA gain can be selected in four steps (between 0 and
-20dB relative to the highest gain) according to RF signal
strength. It can be useful in an environment with strong
interferers.
Baseband Filters
The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.
An appropriate bandwidth can be chosen to accommodate
various FSK deviation, data rate and crystal tolerance
requirements. The filter structure is 7
th order Butterworth low-
pass with 40 dB suppression at 2 · BW frequency. Offset
cancellation is done by using a high-pass filter with a cut-off
frequency below 7 kHz.
Full Baseband Amplifier Transfer Function
BW=67kHz
Data Filtering and Clock Recovery
Output data filtering can be completed by an external capacitor
or by using digital filtering according to the final application.
Analog operation: The filter is an RC type low-pass filter followed
by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
integrated on the chip. An (external) capacitor can be chosen
according to the actual bit rate. In this mode, the receiver can
handle up to 256 kbps data rate. The FIFO cannot be used in this
mode and clock is not provided for the demodulated data.
Digital operation: A digital filter is used with a clock frequency at
29 times the bit rate. In this mode, there is a clock recovery
circuit (CR), which can provide synchronized clock to the data.
Using this clock the received data can fill a FIFO. The CR has
three operation modes: fast, slow, and automatic. In slow mode,
its noise immunity is very high, but it has slower settling time and
requires more accurate data timing than in fast mode. In
automatic mode, the CR automatically changes between fast and
slow mode. The CR starts in fast mode, then after locking, it
automatically switches to slow mode
(Only the digital data filter and the clock recovery use the bit rate
clock. For analog operation, there is no need for setting the
correct bit rate.)