Silicon Image SiliconDrive SSDS00-3650H-R - Manual (Page 38)

S ILICON S YSTEMS P ROPRIETARY
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P AGE 26 J UNE 17, 2008 D OCUMENT : 3650H-02DSR
SSD-H XXX (I)-3650 D ATA S HEET ATA R EGISTERS
D EVICE A DDRESS R EGISTER
The Device Address register is used to maintain compatibility with ATA disk
drive interfaces.
Table 28: Device Address Register
Operation D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Read/Write - nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0
Default Value 0 0 1 1 1 1 1 0
Bit(s) Description
7 Reserved bit.
6 Write Gate (nWTG). Low when a write to the device is in process.
5-2 nHS3 to nHS0. The negated binary address of the currently selected
head.
1 nDS1. Low when drive 1 is selected and active.
0 nDS0. Low when drive 0 is selected and active.