Datasheet – SMSC LAN9420 User Manual
Page 112
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
112
SMSC LAN9420/LAN9420i
DATASHEET
1
Start/Stop Receive (SR)
When set, the Receive Process is placed in the Running state. The DMA
Controller attempts to acquire the descriptor from the receive list and
process incoming frames.
Descriptor acquisition is attempted from the current position in the list,
which is the address set by the RX_BASE_ADDR or the position retained
when the receive process was previously stopped. If no descriptor is owned
by the DMA Controller, the Receive process enters the Suspended state
and the Receive Buffer Unavailable (DMAC_STATUS bit [7]) is set.
The Start Reception command is effective only when the reception process
has stopped. If the command was issued before setting the
RX_BASE_ADDR, the DMA Controller’s behavior will be undefined. When
cleared, the Receive process enters the Stopped state after completing the
reception of the current frame. The next descriptor position in the receive
list is saved, and becomes the current position after the Receive process is
restarted. The Stop Reception command is effective only when the Receive
process is in the Running or Suspended State.
Note:
In order to successfully enable the receive path, the RX DMAC
must be enabled (by setting SR) prior to enabling the receiver (by
setting the RXEN bit of the
).
Note:
In order to successfully disable the receive path, the receiver must
be disabled (by clearing the RXEN bit of the
) prior to disabling the RX DMAC (by clearing SR).
Otherwise, RX DMA will not stop (DMAC_STATUS will continue to
show the Receive Process State (RS) as Running and Receive
Process Stopped (RPS) does not assert).
R/W
0b
0
RESERVED
RO
-
BITS
DESCRIPTION
TYPE
DEFAULT