SMSC LAN9420 User Manual
Page 115
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
115
Revision 1.22 (09-25-08)
DATASHEET
4.3.9
Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)
The DMAC maintains two counters to track the number of missed frames during a receive operation.
The MISS_FRAME_CNTR register reports the current value of these counters and their overflow bits.
Offset:
0020h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:29
RESERVED
RO
-
28
MIL RX FIFO Full Counter Overflow (MIL_OVER)
Overflow bit for the MIL_FIFO_FULL counter. This bit is automatically
cleared on a read.
RC
0b
27:17
MIL RX FIFO Full Counter (MIL_FIFO_FULL)
This field indicates the number of frames missed due a MIL RX FIFO full
condition. This counter is automatically cleared on a read.
RC
000h
16
RX Buffer Unavailable Counter Overflow (UNAV_OVER)
Overflow bit for the RX_BUFF_UNAV counter. This bit is automatically
cleared on a read.
RC
0b
15:0
RX Buffer Unavailable Counter (RX_BUFF_UNAV)
This field indicates the number of frames missed due to receive buffers
being unavailable. This counter is incremented each time the DMAC
discards an incoming frame. This counter is automatically cleared on a
read.
RC
0000h