Checksum offload engine control register (coe_cr), Checksum offload, Engine control register (coe_cr) – SMSC LAN9420 User Manual
Page 134
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
134
SMSC LAN9420/LAN9420i
DATASHEET
4.4.13Checksum Offload Engine Control Register (COE_CR)
This register controls the RX and TX checksum offload engines
.
Offset:
00B0h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:17
RESERVED
RO
-
16
TX Checksum Offload Engine Enable (TX_COE_EN)
The COE_EN may only be changed if the TX path is disabled. If it is desired
to disable the TX_COE_EN during run time, it is safe to do so only after the
MAC is disabled and the MIL is empty.
0: The TXCOE is bypassed
1: The TXCOE is enabled
R/W
0b
15:2
RESERVED
RO
-
1
RX Checksum Offload Engine Mode (RX_COE_MODE)
This register indicates whether the COE will check for VLAN tags or a
SNAP header prior to beginning its checksum calculation. In its default
mode, the calculation will always begin 14 bytes into the frame.
The COE_MODE may only be changed if the RX path is disabled. If it is
desired to change this value during run time, it is safe to do so only after
the MAC is disabled and the MIL is empty.
0: Begin checksum calculation after first 14 bytes of Ethernet Frame
1: Begin checksum calculation at start of L3 packet by adjusting for VLAN
tags and/or SNAP header.
R/W
0b
0
RX Checksum Offload Engine Enable (RX_COE_EN)
The COE_EN may only be changed if the RX path is disabled. If it is
desired to disable the COE_EN during run time, it is safe to do so only after
the MAC is disabled and the MIL is empty.
0: The RXCOE is bypassed
1: The RXCOE is enabled
Note:
When the RXCOE is enabled, automatic pad stripping must be
disabled (PADSTR bit of the
)
and vice versa. These functions cannot be enabled
simultaneously.
R/W
0b