8 eeprom timing, Figure 5.4 eeprom timing, Table 5.12 eeprom timing values – SMSC LAN9420 User Manual
Page 165: Eeprom timing, Refer to, Datasheet
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
165
Revision 1.22 (09-25-08)
DATASHEET
5.8
EEPROM Timing
The following specifies the EEPROM timing requirements for LAN9420/LAN9420i:
Figure 5.4 EEPROM Timing
Table 5.12 EEPROM Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ckcyc
EECLK Cycle time
1110
1130
ns
t
ckh
EECLK High time
550
570
ns
t
ckl
EECLK Low time
550
570
ns
t
cshckh
EECS high before rising edge of EECLK
1070
ns
t
cklcsl
EECLK falling edge to EECS low
30
ns
t
dvckh
EEDIO valid before rising edge of EECLK
(OUTPUT)
550
ns
t
ckhdis
EEDIO disable after rising edge EECLK
(OUTPUT)
550
ns
t
dsckh
EEDIO setup to rising edge of EECLK (INPUT)
90
ns
t
dhckh
EEDIO hold after rising edge of EECLK
(INPUT)
0
ns
t
ckldis
EECLK low to data disable (OUTPUT)
580
ns
t
cshdv
EEDIO valid after EECS high (VERIFY)
600
ns
t
dhcsl
EEDIO hold after EECS low (VERIFY)
0
ns
t
csl
EECS low
1070
ns
EECLK
EEDO
EEDI
EECS
t
ckldis
t
cshckh
EEDI (VERIFY)
t
ckh
t
ckl
t
ckcyc
t
cklcsl
t
csl
t
dvckh
t
ckhdis
t
dsckh
t
dhckh
t
dhcsl
t
cshdv