SMSC LAN9420 - Manual (Page 169)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 169 Revision 1.22 (09-25-08)
DATASHEET
Chapter 7 Revision History
Table 7.1 Customer Revision History
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION
Rev. 1.22
(09-23-08)
Added PCI SIG certification logo to cover
Rev. 1.21
(07-30-08)
Figure 1.2
LAN9420/LAN9420i Internal
Block Diagram on page 11 Fixed error: Changed “To option..” text to
“(optional)” and moved it to the end of the
descriptions.
Figure 1.2
LAN9420/LAN9420i Internal
Block Diagram on page 11 - Changed “To option..” text to “(optional)” and
moved it to the end of the descriptions.
- Removed “To” from “To Ethernet”.
- Placed bi-directional arrows on EEPROM,
GPIO/LED, and PHY blocks.
Section 4.5.5, "Auto
Negotiation Advertisement,"
on page 140 Changed bits 9 and 15 to RESERVED with a
default value of 0b.
Table 4.10, “Standard PCI
Header Registers
Supported,” on page 150 Added note to default value of Revision ID stating
that the default value is dependent on device
revision.
Table 4.10, “Standard PCI
Header Registers
Supported,” on page 150 Changed default values of Min_Gnt and Max_Lat
to 02h and 04h, respectively.
Section 3.5.5.1, "RX
Checksum Calculation," on
page 63 Changed last line of RX checksum calculation to
“checksum = [B1, B0] + C0 + [B3, B2] + C1 + …
+ [0, BN] + CN-1”
Section 3.5.4, "Wakeup
Frame Detection," on
page 57
, Section 4.4.1,
"MAC Control Register
(MAC_CR)," on page 119
Added note: “When wake-up frame detection is
enabled via the WUEN bit of the
Wakeup Control
and Status Register (WUCSR) , a broadcast wake-
up frame will wake-up the device despite the state
of the Disable Broadcast (BCAST) bit in the
MAC
Control Register (MAC_CR) . “
Section 4.4.12, "Wakeup
Control and Status Register
(WUCSR)," on page 133 Corrected GUE bit description to state: “....A global
unicast frame has the MAC Address [0] bit set to
0.”
Section 5.9, "Clock Circuit,"
on page 166 Updated Drive Level from 0.5mW to 300uW.
Section 4.5.5, "Auto
Negotiation Advertisement,"
on page 140 Fixed Pause Operation bit definitions to:
00 No PAUSE
01 Symmetric PAUSE
10 Asymmetric PAUSE
11 Advertise support for both symmetric PAUSE
and Asymmetric PAUSE
Added note stating: When both symmetric PAUSE
and asymmetric PAUSE support are advertised
(value of 11), the device will only be configured to,
at most, one of the two settings upon auto-
negotiation completion.