Figure 3.5 interrupt generation, 3 system control block (scb), 1 interrupt controller – SMSC LAN9420 User Manual
Page 28: System control block (scb) 3.3.1, Interrupt controller, System control block (scb), For sources, Figure 3.5, Datasheet, Interrupt controller pcib
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
28
SMSC LAN9420/LAN9420i
DATASHEET
Bit 3 of the PCI Device Status Register. The PCI Device Status Register and PCI Device Command
Register are standard registers in PCI Configuration Space. Please refer to
Configuration Space CSR (CONFIG CSR)," on page 149
for details.
3.3
System Control Block (SCB)
The System Control Block includes an interrupt controller, wake detection logic, a general-purpose
timer, a free-run counter and system control and status registers.
Interrupt Controller: The interrupt controller can be programmed to interrupt the Host system
applications on the occurrence of various events. The interrupt is routed to the Host system via the
PCIB.
Wake Detection Logic: This logic detects the occurrence of an enabled wake event and asserts the
PCI nPME signal, if enabled.
General Purpose Timer (GPT): The general purpose timer can be configured to generate a system
interrupt upon timeout.
Free-Run Counter (FRC): A 32-bit free-running counter with a 160 ns resolution.
EEPROM Controller (EPC): An optional, external, Serial EEPROM may be used to store the default
values for the MAC address, PCI Subsystem ID, and PCI Subsystem Vendor ID. In addition, it may
also be used for general data storage. The EEPROM controller provides LAN9420/LAN9420i access
to the EEPROM and permits the Host to read, write and erase its contents.
System Control and Status Registers (SCSR): These registers control system functions that are not
specific to the DMAC, MAC or PHY.
3.3.1
Interrupt Controller
The Interrupt Controller handles the routing of all internal interrupt sources. Interrupts enter the
controller from various modules within LAN9420/LAN9420i. The Interrupt Controller drives the interrupt
request (IRQ) output to the PCI Bridge. The Interrupt Controller is capable of generating PCI interrupts
on detection of the following internal events:
DMAC interrupt request (DMAC_INT)
PHY interrupt request (PHY_INT)
Figure 3.5 Interrupt Generation
Interrupt
Controller
PCIB
Bit 10
PCI Device
Command Register
RW
IRQ
Bit 3
PCI Device
Status Register
nINT
(To Host)