SMSC LAN9420 - Manual (Page 50)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 50 SMSC LAN9420/LAN9420i
DATASHEET
Note: The TX and RX processes and paths are independent of each other and can be started or
stopped independently of one another. However, the control sequence required to activate the
RX path must be followed explicitly. The RX DMAC should be activated before the MAC’s
receiver. Failure to do so may lead to unpredictable results and untoward operation.
3.4.4 Transmit Operation
Transmission proceeds as follows:
1. The Host system sets up the Transmit Descriptor (TDES0-3) and sets the OWN bit (TDES0[31]).
2. Once set to the running state, the DMA controller reads the Host memory buffer to collect the first
descriptor. The starting address of the first descriptor is read from the TX_BASE_ADDR register.
3. Data transfer begins, and continues until the last DWORD of the frame is transferred. A frame may
traverse multiple descriptors. Frames must be delimited by the first segment (FS - TDES1[29]) and
last segment (LS - TDES1[30]) respectively.
4. When the frame transmission is completed, status is written into TDES0 with the OWN bit reset to
0. If the DMAC detects a descriptor flag that is owned by the Host, or if an error condition occurs,
the transmit engine enters into the suspended state and both (TU) Transmit Buffer Unavailable and
(NIS) Normal Interrupt Summary bits are set. Transmit Interrupt (TI) is set after completing
transmission of a frame that has an interrupt, and on completion the last descriptor (TDES0[30]) is
set. A new frame transmission will move the DMA from the Suspended state.
3.4.5 Receive Operation
The general sequence of events for reception of a frame is as follows:
1. The Host system sets up the receive descriptors RDES0-3 and sets the OWN bit (RDES0[31]). The
Host system polls the OWN bit and, once it recognizes a descriptor for itself, it can begin working
on the descriptor.
2. Once set to the running state, the DMA controller reads the Host memory buffer to collect the first
descriptor. The starting address of the first descriptor is read from the RX_BASE_ADDR register.
3. Data transfer begins, and continues until the last DWORD of the frame is transferred. A frame may
traverse multiple descriptors. The DMA controller delimits the frames by setting the First Segment
(RDES0[9]) and Last Segment (RDES0[8]) respectively. As a buffer is filled, or when the Last
Segment is transferred to the Host memory buffer, the descriptor of that buffer is closed (OWN bit
is cleared).
4. When a frame transfer is completed, the status field in RDES0 of the last descriptor is updated and
the OWN bit reset to 0, and the Receive Interrupt (RI) is then set. The receive engine continues
to fetch the next descriptor and repeat the process unless it encounters a descriptor marked as
being owned by the Host system. If this occurs, the Receive Buffer Unavailable bit (RU) is set and
the receive engine enters the suspended state. If a new frame arrives while the receive engine is
in the suspended state, the DMA controller re-fetches the current descriptor. If the descriptor is now
owned by the DMAC, the receive process continues. If the descriptor is still owned by the Host
system, the frame is discarded and DMAC re-enters the suspend state. This process is repeated
for each received frame.
5. The reception of a new frame will move the RX engine from the suspend state.
Note: Oversized RX packets must not cross from one buffer to another unless either the starting
address of the 2nd buffer is DWORD aligned, or the oversized packet is to be discarded.
3.4.6 Receive Descriptor Acquisition
The receive engine always attempts to acquire an extra descriptor in the anticipation of an incoming
frame. Descriptor acquisition is attempted if any of the following conditions are satisfied:
„ When the (SR) Start/Stop Receive bit (bit 1 of DMAC_CONTROL) sets immediately after being
placed in the running state