SMSC LAN9420 - Manual (Page 71)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 71 Revision 1.22 (09-25-08)
DATASHEET
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits
of the Link Code Word). It advertises its technology ability according to the bits set in register 4 of the
SMI registers.
There are 4 possible matches of the technology abilities. In the order of priority these are:
„ 100M full-duplex (Highest priority)
„ 100M half-duplex
„ 10M full-duplex
„ 10M half-duplex
If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable
of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link
partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest
performance operation.
Once a capability match has been determined, the link code words are repeated with the acknowledge
bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation
to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received.
Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing
register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new
abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0,
bit 12.
LAN9420/LAN9420i does not support “Next Page" capability.
3.6.6 Parallel Detection
If LAN9420/LAN9420i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are
detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M
Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This
ability is known as “Parallel Detection”. This feature ensures inter operability with legacy link partners.
If a link is formed via parallel detection, then bit 0 in register 6 is cleared to indicate that the Link
Partner is not capable of auto-negotiation. The Ethernet MAC has access to this information via the
management interface. If a fault occurs during parallel detection, bit 4 of register 6 is set.
Register 5 is used to store the Link Partner Ability information, which is coded in the received FLPs.
If the Link Partner is not auto-negotiation capable, then register 5 is updated after completion of parallel
detection to reflect the speed capability of the Link Partner.
3.6.6.1 Re-starting Auto-negotiation
Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also re-
start if the link is broken at any time. A broken link is caused by signal loss. This may occur because
of a cable break, or because of an interruption in the signal transmitted by the Link Partner. Auto-
negotiation resumes in an attempt to determine the new link configuration.
If the management entity re-starts Auto-negotiation by writing to bit 9 of the control register,
LAN9420/LAN9420i will respond by stopping all transmission/receiving operations. Once the
break_link_timer is done, in the Auto-negotiation state-machine (approximately 1200ms) the auto-
negotiation will re-start. The Link Partner will have also dropped the link due to lack of a received
signal, so it too will resume auto-negotiation.
3.6.6.2 Disabling Auto-negotiation
Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its
speed of operation to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex).
The speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled.