SMSC LAN9420 - Manual (Page 83)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 83 Revision 1.22 (09-25-08)
DATASHEET
Chapter 4 Register Descriptions
The registers are partitioned into five groups. The first group is the System Control and Status
Registers (SCSR). The second group is the DMA Control and Status Registers (DCSR). These
registers are located within the DMAC and are used to control DMA-specific functions. The third group
is the MAC Control and Status Registers (MCSR). These registers handle all control and status directly
related to MAC function and are located within the MAC. The fourth group are the PHY control
registers. These registers reside within the PHY, and are accessed indirectly through MCSR within the
MAC. The fifth set of registers is the PCI Configuration Space CSR (CONFIG CSR) registers. Each
group is described separately within this section.
Figure 4.1 illustrates the memory map for the first three register groups. The Base Address (BA) of the
map is determined by BAR3/BAR4, contained within the standard PCI Header Registers of the
CONFIG CSR. See
Table 4.10, “Standard PCI Header Registers Supported,” on page 150 for details.
In the case of BAR3, BA may be either the address of the lower (for little endian access) or upper (for
big endian access) 512 byte segment of the 1KB MemSpace. See
Figure 3.3 CSR Double Endian
Mapping on page 27 for details.