SMSC LAN9420 - Manual (Page 97)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 97 Revision 1.22 (09-25-08)
DATASHEET
4.2.9 Power Management Control Register (PMT_CTRL)
This register controls the wake event detection features. This register also controls the SCSR soft reset
to the PHY.
Note: If waking from a reduced-power state causes the assertion of a device reset, this register will
be cleared.
Offset: 00E0h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:11 RESERVED RO -
10 PHY Reset (PHY_RST)
Writing a ‘1’ to this bit resets the PHY. The internal logic automatically holds
the PHY reset for a minimum of 100us. When the PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is high. SC 0b
9 Wake-On-Lan Wakeup Enable (WOL_EN)
When set, the MAC Wake Detect signal is enabled as a wake event and
will set the PME_STATUS in the PCI_PMCSR. The MAC Wake Detect
signal can be programmed for assertion upon detection of a Wakeup Frame
or Magic Packet. R/W 0b
8 Energy-Detect Wakeup Enable (ED_EN)
When set, the PHY Interrupt signal is enabled as a wake event and will set
the PME_STATUS bit in the PCI_PMCSR. The PHY interrupt can be
programmed for assertion upon detection of a link status change (Energy
Detect) event. R/W 0b
7:5 RESERVED RO -
4:3 Wakeup Status (WUPS)
This field indicates the cause of the last wake event. This field is cleared
by writing ‘1’ to the currently set bit(s). WUPS is encoded as follows:
00b – No wakeup event detected
x1b – PHY interrupt (Energy-Detect)
1xb – MAC wakeup event (Wakeup Frame or Magic Packet)
Note: If waking from a reduced-power state causes the assertion of a
device reset, the wakeup status bits will be cleared.
R/WC 00b
2:0 RESERVED RO 000b