Lantronix DSTni-EX - Manual (Page 28)

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− The IFLG is set and the Status register contains B8h.
− After the last transmission byte loads in the Data register, clear
AAK when IFLG clears.
− After the last byte is transmitted, the IFLG is set and the Status
register contains C8h.
− The I 2 C controller returns to the idle state and the AAK bit must be
set to 1 before slave mode can be entered again.
If the I 2 C controller does not receive an acknowledge:
− The IFLG is set.
− The Status register contains C0h.
− The I 2 C controller returns to the idle state.
4. If the I 2 C detects a STOP condition after an acknowledge bit, it returns to the idle state.
Slave Receive Mode
In slave receive mode, a number of data bytes are received from a master transmitter.
The I 2 C controller enters slave receive mode when it receives its own slave address and write
bit (least-significant bit = 0) after a START condition. The I 2 C controller then transmits an
acknowledge bit and sets the IFLG bit in the Control register. The Status register status code is
60h.
The I 2 C controller also enters slave receive mode when it receives the general call address 00h
(if the GCE bit in the Slave Address register is set). The status code is 70h.
Note: If the I
2
C controller has an extended slave address (signified by F0h - F7h in the Slave
Address register), it transmits an acknowledge after receiving the first address byte, but does
not generate an interrupt; the IFLG is not set and the status does not change. Only after
receiving the second address byte does the I
2
C controller generate an interrupt and set the
IFLG bit and the status code as described above.
The I 2 C controller also enters slave transmit mode directly from a master mode if arbitration is
lost during address transmission, and both the slave address and write bit (or general call
address if bit GCE in the Slave Address register is set to one) are received. The status code in
the Status register is 68h if the slave address is received or 78h if the general call address is
received. The IFLG bit must clear to 0 to allow the data transfer to continue.
If the AAK bit in the Control register is set to 1:
1. Receiving each byte transmits an acknowledge bit (LOW level on SDA) and sets the IFLG
bit.
2. The Status register contains status code 80h (or 90h if slave receive mode was entered
with the general call address).
3. The received data byte can be read from the Data register and the IFLG bit must clear to
allow the transfer to continue.
4. When the STOP condition or repeated START condition is detected after the acknowledge
bit, the IFLG bit is set and the Status register contains status code A0h.
If the AAK bit clears to zero during a transfer, the I
2 C controller transfers a not acknowledge bit
(high level on SDA) after the next byte is received and sets the IFLG bit. The Status register
contains status code 88h (or 98h if slave receive mode was entered with the general call
address). When the IFLG bit clears to zero, the I
2 C controller returns to the idle state.