Renesas M65881AFP - Manual (Page 11)

Rev.1.00 2003.05.08 page 11 of 23
M65881AFP
HPOUTL1, HPOUTL2, HPOUTR1 and HPOUTR2 are output pins for Headphone output.
PWM output modulated
∆Σ
output data to pulse width.
The Phase of PWM Output for Power Stage and PWM Output for Headphone.
The output for Headphone is reverse phase as output for Power.
Moreover, it is possible to set L1 and R1 output same phase by serial control the system 1 mode,
bit24= "H"( PWMHP ).
In addition, NSPMUTE, PGMUTE and CHSEL are set in common PWM for Power
and PWM for Headphone, and as for CHRSEL flag is set as a function of only PWM for Power.
( Refer to previous page "Table of PWM control" for details ).
9. NSPMUTE
NSPMUTE pin sets to PWM Output to Duty 50% Mute.
L: PWM Output 50% Mute
H: Mute release
10. INIT
INIT is the pin for reset to all functions of M65881AFP.
"L" level: (1) Clear of data memory, (2) Initialization of a serial control setting
(3) PWM Output Duty 50% Mute
( " L" period needs more than 5msec.)
"H" level : Usual operation.
*The rise edge from "L" to "H": Re-synchronization are operated, which is same at serial control SYNC
function. (system2 mode bit6)
11. TEST1, TEST2
TEST1 and TEST2 pins are test input for factory shipping test of M65881AFP.
TEST1 and TEST2 pins must be tied to "L" level on usual operation.
12. Power supply and GND
Power supply and GND routes have a following 6 isolated lines.
(1) VddL, VssL,VddR, VssR, VssLR
VddL, VssL,VddR, VssR and VssLR pins are Power supply and GND for PWM Output buffer.
Lch and Rch have a independent power supply and GND. Power supply must be fixed at 3.3V.
(2) HPVddL, HPVssL, HPVddR, HPVssR
HPVddL, HPVssL, HPVddR and HPVssR pins are Power supply and GND of PWM Output
buffer for Headphone. Lch and Rch have a independent power supply and GND.
Power supply must be fixed at 3.3V.
(3) XVdd, XVss
XVdd and XVss are Power supply and GND for XfsoIN clock input block.
Power supply voltage must be fixed at 3.3V.
(4) XOVdd, XOVss
XOVdd and XOVss are Power supply and GND for XfsoOUT Clock Output.
Power supply voltage must be fixed at 3.3V
(5) DVdd, DVss
DVdd, DVss are Power supply and GND for internal digital block.
Power supply voltage must be fixed at 1.8V.
(6) BFVdd, BFVss
BFVdd and BFVss are Power and GND for input/output buffer (except for PWM block
and clock buffer). Power supply voltage must be fixed at 3.3V.
8. HPOUTL1, HPOUTL2, HPOUTR1, HPOUTR2