Texas Instruments TMS320DM36X User Manual
User's guide
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Table of contents
Document Outline
- TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC)
- Table of Contents
- Preface
- 1 Introduction
- 2 Architecture
- 2.1 Clock Control
- 2.2 Memory Map
- 2.3 Signal Descriptions
- 2.4 Pin Multiplexing
- 2.5 Ethernet Protocol Overview
- 2.6 Programming Interface
- 2.6.1 Packet Buffer Descriptors
- 2.6.2 Transmit and Receive Descriptor Queues
- 2.6.3 Transmit and Receive EMAC Interrupts
- 2.6.4 Transmit Buffer Descriptor Format
- 2.6.4.1 Next Descriptor Pointer
- 2.6.4.2 Buffer Pointer
- 2.6.4.3 Buffer Offset
- 2.6.4.4 Buffer Length
- 2.6.4.5 Packet Length
- 2.6.4.6 Start of Packet (SOP) Flag
- 2.6.4.7 End of Packet (EOP) Flag
- 2.6.4.8 Ownership (OWNER) Flag
- 2.6.4.9 End of Queue (EOQ) Flag
- 2.6.4.10 Teardown Complete (TDOWNCMPLT) Flag
- 2.6.4.11 Pass CRC (PASSCRC) Flag
- 2.6.5 Receive Buffer Descriptor Format
- 2.6.5.1 Next Descriptor Pointer
- 2.6.5.2 Buffer Pointer
- 2.6.5.3 Buffer Offset
- 2.6.5.4 Buffer Length
- 2.6.5.5 Packet Length
- 2.6.5.6 Start of Packet (SOP) Flag
- 2.6.5.7 End of Packet (EOP) Flag
- 2.6.5.8 Ownership (OWNER) Flag
- 2.6.5.9 End of Queue (EOQ) Flag
- 2.6.5.10 Teardown Complete (TDOWNCMPLT) Flag
- 2.6.5.11 Pass CRC (PASSCRC) Flag
- 2.6.5.12 Jabber Flag
- 2.6.5.13 Oversize Flag
- 2.6.5.14 Fragment Flag
- 2.6.5.15 Undersized Flag
- 2.6.5.16 Control Flag
- 2.6.5.17 Overrun Flag
- 2.6.5.18 Code Error (CODEERROR) Flag
- 2.6.5.19 Alignment Error (ALIGNERROR) Flag
- 2.6.5.20 CRC Error (CRCERROR) Flag
- 2.6.5.21 No Match (NOMATCH) Flag
- 2.7 EMAC Control Module
- 2.8 MDIO Module
- 2.9 EMAC Module
- 2.9.1 EMAC Module Components
- 2.9.1.1 Receive DMA Engine
- 2.9.1.2 Receive FIFO
- 2.9.1.3 MAC Receiver
- 2.9.1.4 Receive Address
- 2.9.1.5 Transmit DMA Engine
- 2.9.1.6 Transmit FIFO
- 2.9.1.7 MAC Transmitter
- 2.9.1.8 Statistics Logic
- 2.9.1.9 State RAM
- 2.9.1.10 EMAC Interrupt Controller
- 2.9.1.11 Control Registers and Logic
- 2.9.1.12 Clock and Reset Logic
- 2.9.2 EMAC Module Operational Overview
- 2.9.1 EMAC Module Components
- 2.10 Media Independent Interface (MII)
- 2.11 Packet Receive Operation
- 2.12 Packet Transmit Operation
- 2.13 Receive and Transmit Latency
- 2.14 Transfer Node Priority
- 2.15 Reset Considerations
- 2.16 Initialization
- 2.17 Interrupt Support
- 2.18 Power Management
- 2.19 Emulation Considerations
- 3 EMAC Control Module Registers
- 3.1 EMAC Control Module Identification and Version Register (CMIDVER)
- 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET)
- 3.3 EMAC Control Module Emulation Control Register (CMEMCONTROL)
- 3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL)
- 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)
- 3.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
- 3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
- 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)
- 3.9 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)
- 3.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
- 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
- 3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT)
- 3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX)
- 3.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX)
- 4 MDIO Registers
- 4.1 MDIO Version Register (VERSION)
- 4.2 MDIO Control Register (CONTROL)
- 4.3 PHY Acknowledge Status Register (ALIVE)
- 4.4 PHY Link Status Register (LINK)
- 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
- 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
- 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
- 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
- 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
- 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
- 4.11 MDIO User Access Register 0 (USERACCESS0)
- 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)
- 4.13 MDIO User Access Register 1 (USERACCESS1)
- 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)
- 5 Ethernet Media Access Controller (EMAC) Registers
- 5.1 Transmit Identification and Version Register (TXIDVER)
- 5.2 Transmit Control Register (TXCONTROL)
- 5.3 Transmit Teardown Register (TXTEARDOWN)
- 5.4 Receive Identification and Version Register (RXIDVER)
- 5.5 Receive Control Register (RXCONTROL)
- 5.6 Receive Teardown Register (RXTEARDOWN)
- 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
- 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
- 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)
- 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
- 5.11 MAC Input Vector Register (MACINVECTOR)
- 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)
- 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
- 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
- 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
- 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
- 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
- 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
- 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
- 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
- 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
- 5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
- 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
- 5.24 Receive Maximum Length Register (RXMAXLEN)
- 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)
- 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
- 5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)
- 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)
- 5.29 MAC Control Register (MACCONTROL)
- 5.30 MAC Status Register (MACSTATUS)
- 5.31 Emulation Control Register (EMCONTROL)
- 5.32 FIFO Control Register (FIFOCONTROL)
- 5.33 MAC Configuration Register (MACCONFIG)
- 5.34 Soft Reset Register (SOFTRESET)
- 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)
- 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)
- 5.37 MAC Hash Address Register 1 (MACHASH1)
- 5.38 MAC Hash Address Register 2 (MACHASH2)
- 5.39 Back Off Test Register (BOFFTEST)
- 5.40 Transmit Pacing Algorithm Test Register (TPACETEST)
- 5.41 Receive Pause Timer Register (RXPAUSE)
- 5.42 Transmit Pause Timer Register (TXPAUSE)
- 5.43 MAC Address Low Bytes Register (MACADDRLO)
- 5.44 MAC Address High Bytes Register (MACADDRHI)
- 5.45 MAC Index Register (MACINDEX)
- 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)
- 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)
- 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)
- 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)
- 5.50 Network Statistics Registers
- 5.50.1 Good Receive Frames Register (RXGOODFRAMES)
- 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)
- 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)
- 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)
- 5.50.5 Receive CRC Errors Register (RXCRCERRORS)
- 5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)
- 5.50.7 Receive Oversized Frames Register (RXOVERSIZED)
- 5.50.8 Receive Jabber Frames Register (RXJABBER)
- 5.50.9 Receive Undersized Frames Register (RXUNDERSIZED)
- 5.50.10 Receive Frame Fragments Register (RXFRAGMENTS)
- 5.50.11 Filtered Receive Frames Register (RXFILTERED)
- 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)
- 5.50.13 Receive Octet Frames Register (RXOCTETS)
- 5.50.14 Good Transmit Frames Register (TXGOODFRAMES)
- 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)
- 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)
- 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)
- 5.50.18 Deferred Transmit Frames Register (TXDEFERRED)
- 5.50.19 Transmit Collision Frames Register (TXCOLLISION)
- 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)
- 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)
- 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)
- 5.50.23 Transmit Late Collision Frames Register (TXLATECOLL)
- 5.50.24 Transmit Underrun Error Register (TXUNDERRUN)
- 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)
- 5.50.26 Transmit Octet Frames Register (TXOCTETS)
- 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64)
- 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)
- 5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)
- 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)
- 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)
- 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)
- 5.50.33 Network Octet Frames Register (NETOCTETS)
- 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)
- 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)
- 5.50.36 Receive DMA Overruns Register (RXDMAOVERRUNS)
- Appendix A Glossary
- Appendix B Revision History