Texas Instruments TMS320DM36X - Manual (Page 54)

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2.16.4 EMAC Module Initialization
The EMAC module is used to send and receive data packets over the network. This is done by
maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must
also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the
work in developing an application or device driver for Ethernet is programming this module.
The following is the initialization procedure a device driver would follow to get the EMAC to the state
where it is ready to receive and send Ethernet packets. Some of these steps are not necessary when
performed immediately after device reset.
1. If enabled, clear the device interrupt enable in the EMAC control module interrupt control registers
(CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN).
2. Clear the MAC control register (MACCONTROL), receive control register (RXCONTROL), and
transmit control register (TXCONTROL) (not necessary immediately after reset).
3. Initialize all 16 header descriptor pointer registers (RXnHDP and TXnHDP) to 0.
4. Clear all 36 statistics registers by writing 0 (not necessary immediately after reset).
5. Setup the local Ethernet MAC address by programming the MAC index register (MACINDEX), MAC
address high bytes register (MACADDRHI), and MAC address low bytes register (MACADDRLO).
Be sure to program all eight MAC addresses - whether the receive channel is to be enabled or not.
Duplicate the same MAC address across all unused channels. When using more than one receive
channel, start with channel 0 and progress upwards.
6. Initialize the receive channel n free buffer count registers (RXnFREEBUFFER), receive channel n
flow control threshold register (RXnFLOWTHRESH), and receive filter low priority frame threshold
register (RXFILTERLOWTHRESH), if buffer flow control is to be enabled.
7. Most device drivers open with no multicast addresses, so clear the MAC address hash registers
(MACHASH1 and MACHASH2) to 0.
8. Write the receive buffer offset register (RXBUFFEROFFSET) value (typically zero).
9. Initially clear all unicast channels by writing FFh to the receive unicast clear register
(RXUNICASTCLEAR). If unicast is desired, it can be enabled now by writing the receive unicast set
register (RXUNICASTSET). Some drivers will default to unicast on device open while others will not.
10. Setup the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) with
an initial configuration. The configuration is based on the current receive filter settings of the device
driver. Some drivers may enable things like broadcast and multicast packets immediately, while
others may not.
11. Set the appropriate configuration bits in MACCONTROL (do not set the MIIEN bit yet).
12. Clear all unused channel interrupt bits by writing the receive interrupt mask clear register
(RXINTMASKCLEAR) and the transmit interrupt mask clear register (TXINTMASKCLEAR).
13. Enable the receive and transmit channel interrupt bits in the receive interrupt mask set register
(RXINTMASKSET) and the transmit interrupt mask set register (TXINTMASKSET) for the channels
to be used, and enable the HOSTMASK and STATMASK bits using the MAC interrupt mask set
register (MACINTMASKSET).
14. Initialize the receive and transmit descriptor list queues.
15. Prepare receive by writing a pointer to the head of the receive buffer descriptor list to RXnHDP.
16. Enable the receive and transmit DMA controllers by setting the RXEN bit in RXCONTROL and the
TXEN bit in TXCONTROL. Then set the MIIEN bit in MACCONTROL.
17. Enable the device interrupt in the EMAC control module interrupt control registers
(CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN).
54 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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