Texas Instruments TMS320C642x DSP User Manual
User's guide
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Table of contents
Document Outline
- Table of Contents
- Preface
- 1 Device Clocking
- 2 PLL Controller
- 2.1 PLL Module
- 2.2 PLL1 Control
- 2.3 PLL2 Control
- 2.4 PLL Controller Registers
- 2.4.1 Peripheral ID Register (PID)
- 2.4.2 Reset Type Status Register (RSTYPE)
- 2.4.3 PLL Control Register (PLLCTL)
- 2.4.4 PLL Multiplier Control Register (PLLM)
- 2.4.5 PLL Controller Divider 1 Register (PLLDIV1)
- 2.4.6 PLL Controller Divider 2 Register (PLLDIV2)
- 2.4.7 PLL Controller Divider 3 Register (PLLDIV3)
- 2.4.8 Oscillator Divider 1 Register (OSCDIV1)
- 2.4.9 Bypass Divider Register (BPDIV)
- 2.4.10 PLL Controller Command Register (PLLCMD)
- 2.4.11 PLL Controller Status Register (PLLSTAT)
- 2.4.12 PLL Controller Clock Align Control Register (ALNCTL)
- 2.4.13 PLLDIV Ratio Change Status Register (DCHANGE)
- 2.4.14 Clock Enable Control Register (CKEN)
- 2.4.15 Clock Status Register (CKSTAT)
- 2.4.16 SYSCLK Status Register (SYSTAT)
- Appendix A Revision History