3 ddr2/emif clock, 05v) – Texas Instruments TMS320C642x DSP User Manual
Page 9
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1.2.3
DDR2/EMIF Clock
Device Clocking
The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from the
PLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of the
core clock rates to save power while maintaining the required minimum clock rate (125 MHZ) for DDR2.
PLL2 must be configured to output a 2
×
clock to the DDR2 PHY interface.
All of the following frequency ranges and multiplier/divider ratios in the device-specific data manual must
be adhered to when configuring PLL2:
•
Input clock frequency range (MXI/CLKIN)
•
PLL2 multiplier (PLLM) range
•
PLL2 output (PLLOUT) frequency range based on core voltage (1.05V or 1.2V) of the device
and
show some PLL2/DDR2 clock rates assuming a MXI/CLKIN frequency of 25 MHZ.
Table 3. Example PLL2 Frequencies (Core Voltage = 1.2V)
PLL2 PLLOUT Freq
SYSCLK1
PLL2 Multiplier
(MHZ)
Divider
(1)
PHY [2
×
clock] (MHZ)
DDR2 Clock (MHZ)
20
500.0
2
250.0
125.0
21
525.0
2
262.5
131.3
22
550.0
2
275.0
137.5
23
575.0
2
287.5
143.8
24
600.0
2
300.0
150.0
25
625.0
2
312.5
156.3
26
650.0
2
325.0
162.5
30
750.0
3
250.0
125.0
31
775.0
3
258.3
129.2
32
800.0
3
266.7
133.3
(1)
The RATIO bit in PLLDIVn is programmed as Divider - 1. For example, for SYSCLK1 divider of 3, you should program
PLLDIV1.RATIO = 2.
Table 4. Example PLL2 Frequencies (Core Voltage = 1.05V)
PLL2 PLLOUT Freq
SYSCLK1
PLL2 Multiplier
(MHZ)
Divider
(1)
PHY [2
×
clock] (MHZ)
DDR2 Clock (MHZ)
20
500.0
2
250.0
125.0
21
525.0
2
262.5
131.3
22
550.0
2
275.0
137.5
23
575.0
2
287.5
143.8
24
600.0
2
300.0
150.0
25
625.0
2
312.5
156.3
26
650.0
2
325.0
162.5
(1)
The RATIO bit in PLLDIVn is programmed as Divider - 1. For example, for SYSCLK1 divider of 3, you should program
PLLDIV1.RATIO = 2.
SPRUES0B – December 2007
Phase-Locked Loop Controller (PLLC)
9