Texas Instruments TPS2151 - Manual (Page 11)

Schematic of the EVM
2-3 Schematic, Bill of Materials, Layout, and Setup
Only C2, C4, C5, C6, C8, R2, and R3 are essential for the TPS2151 to function
properly. The rest of the components on the EVM are used for different
evaluations of the device. To evaluate the power switch inrush current, a large
capacitor C9 can be added on the EVM.
In order to discharge SW_OUT and LDO_OUT quickly, JP4 and JP5 are
shorted through jumpers on this EVM. Designers may unplug the jumpers and
find the difference. Based on the schematic, the following configurations can
be set by switches (S1 and S2), and jumpers on JP1, JP2, and JP3:
1) Independent operation between the switch and LDO: JP1, JP2, and JP3
are floating (no jumpers). In this configuration, header J1 inputs control the
switch and the LDO, and the device outputs are connected to header J2.
External loads for the switch and the LDO are connected to J2. SW_IN and
LDO_IN are powered by a single supply through J1 or by separate
supplies.
2) Another independent operation: only JP1 is floating (no jumper). A jumper
shorts JP2 from LDO_EN pin to S1 pin, and JP3 is shorted from SW_EN
to S2. In this configuration, slide switches S1 and S2 control the switch and
the LDO. No external control signals are connected to SW_EN and
LDO_EN on header J1. This configuration makes the evaluation easier by
sliding the switches S1 and S2 to control the TPS2151 on and off. SW_IN
and LDO_IN are powered by a single supply through J1, or by separate
supplies.
3) LDO power good to control the power switch: JP1 is still floating, but JP3
is shorted from SW_EN to LDO_PG (no external input SW_EN allowed on
J1) JP2 can be configured the same as either case 1) or case 2). The
power switch of TPS2151 is controlled by the LDO power good output
LDO_PG. The power switch cannot be turned on until the LDO is fully on.
SW_IN and LDO_IN are powered by a single supply through J1 or by
separate supplies.
4) Switch power good to control the LDO: JP1 is still floating, but JP2 is
shorted from LDO_EN to SW_PG (no external input LDO_EN allowed on
J1). JP3 can be configured the same as either case 1) or case 2). Then
the LDO of TPS2151 is controlled by the switch power good output
SW_PG. So the LDO cannot be turned on until the power switch is fully
on. SW_IN and LDO_IN are powered by a single supply through J1 or by
separate supplies.
5) Switch feeding power to the LDO: JP1 is shorted, and JP2 is shorted from
LDO_EN to SW_PG (no external input LDO_EN allowed on J1). JP3 can
be configured the same as either case 1) or case 2). Then the LDO is
connected to the power switch output and controlled by the switch power
good SW_PG. Only one supply is needed for SW_IN through J1, and no
external supply is allowed on LDO_IN at J1.
6) Other configurations can be constructed by further manipulating the
jumpers, slide switches and the input and output headers (J1 and J2).