Texas Instruments DMSoC Analog to Digital Converter Interface TMS320DM36x - Manual (Page 15)

3.7 AD0DAT
3.8 AD1DAT
www.ti.com Registers
Table 7. CHSEL setting for Channel selection
CHSEL Selected Channel
000001b Channel 0
000010b Channel 1
000100b Channel 2
001000b Channel 3
010000b Channel 4
100000b Channel 5
Figure 7. Analog Input Channel Select (CHSEL) Register
31 6 5 0
Reserved CHSEL
R-0 R/W-0x3F
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Analog Input Channel Select (CHSEL) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Any writes to these bit(s) must always have a value of 0.
5-0 CHSEL A/D conversion select bit
0 Analog Input unselected
1 Analog Input selected
The A/D conversion data 0 (AD0DAT) register is shown in Figure 8 and descried in Table 9 .
Figure 8. A/D Conversion Data 0 (AD0DAT) Register
31 10 9 0
Reserved AD0DAT
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. A/D Conversion Data 0 (AD0DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.
9-0 AD0DAT A/D conversion data for channel 0
The A/D conversion data 1 (AD1DAT) register is shown in Figure 9 and described in Table 10 .
Figure 9. A/D Conversion Data 1 (AD1DAT) Register
31 10 9 0
Reserved AD1DAT
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUFI7 – March 2009 Analog to Digital Converter (ADC) Interface 15
Submit Documentation Feedback