Texas Instruments DMSoC Analog to Digital Converter Interface TMS320DM36x - Manual (Page 17)

3.12 AD5DAT
3.13 EMUCTRL
www.ti.com Registers
Table 13. A/D Conversion Data 4 (AD4DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.
9-0 AD4DAT A/D conversion data for channel 4
The A/D conversion data 5 (AD5DAT) register is shown in and described in .
Figure 13. A/D Conversion Data 5 (AD5DAT) Register
31 10 9 0
Reserved AD5DAT
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. A/D Conversion Data 5 (AD5DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.
9-0 AD5DAT A/D conversion data for channel 5
The emulation control (EMUCTRL) register is shown in Figure 14 and described in Table 15 .
Figure 14. Emulation Control (EMUCTRL) Register
31 16
Reserved
R-0
15 3 2 1 0
Reserved RT_SEL SOFT FREE
R-0 R-0 R-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Emulation Control (EMUCTRL) Field Descriptions
Bit Field Value Description
31-2 Reserved Any writes to these bit(s) must always have a value of 0.
2 RT_SEL 0 Support only emulation suspend
1 SOFT Support only soft stop
1 Soft stop: Stop peripheral operations gracefully at the earliest opportunity after the current
application specific processing task is completed.
0 FREE This bit controls whether or not the peripheral will respond to the emulation suspend signal that it
has been programmed to monitor
0 Peripheral suspends according to mode specified by the SOFT bit
1 Peripheral ignores suspend and operates normally
SPRUFI7 – March 2009 Analog to Digital Converter (ADC) Interface 17
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