Vizio P42HDTV10A - Manual (Page 82)

CONFIDENTIAL – DO NOT COPY Page 8-50
File No. SG-0184
BLOCK DIAGRAM
1. Audio sample rate
The master clock forWM8776 supports DAC and ADC audio sampling rates 256fs to 768fs,
where fs is the audio sample frequency (DACLRC or ADCLRC) typically 32KHZ, 44.1KHZ,
48KHZ or 96KHZ (the DAC also supports operation at 128fs and 192fs and 192KHZ sample
rate). The master clock is used to operate the digital filters and the noise shaping circuits.
In slave mode the WM8776 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks) If there is a greater than 32 clocks error the interface is disabled and
ADCLRC/DACLRC for optical performance, although the WM8776 is tolerant of phase
variations or jitter on this clock.
Table shows the typical master clock frequency inputs for the WM8776.