Xilinx ML403 - Manual (Page 27)

Simulation
XAPP979 (v1.0) February 26, 2007 www.xilinx.com 27
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In the first test, which is shown in Figure 30 , the OPB IIC registers are read to verify the correct
reset values. The interrupt registers are written and read. This occurs from 0 - 10 s. Following
this, an arbitration test is run. IIC_AA is initially the bus master, with the write CR_AA 0x0d.
Figure 30: Arbitrartion Lost Test Simulation
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