Reference system specifics – Xilinx ML403 User Manual
Page 4
Reference System Specifics
XAPP979 (v1.0) February 26, 2007
4
R
shows the acknowledge bit on the IIC bus.
shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters
monitor the IIC bus to determine if the bus is active. The bus is inactive when SCL and SDA are
high for a bus free period tBUF of 1.3 us (FAST) or 4.7 us (STD). If two or more masters
monitoring the IIC bus determine that the bus is free and begin a bus transaction
simultaneously, the IIC bus is arbitrated to determine which master owns the bus. The IIC is a
wired AND bus. This means that the bus is HIGH unless any component is driving it LOW.
Masters monitor the bus even after they have started a transaction as the master. If a master is
not driving the IIC bus low and the bus is low, the master knows that another master is driving
the IIC bus. If a master cannot get the SDA or SCL to go high it loses arbitration. When a master
loses arbitration, it stops transmission. The master driving the bus with the last low when the
other master(s) drives high becomes the master of the bus.
Reference
System
Specifics
In addition to the PowerPC405 processor and OPB IIC, this system includes DDR and BRAM
memory on the PLB, and a UART and interrupt controller on the OPB.
provides the
block diagram.
Table 1
provides the address map of the ML403 XC4VFX12. This is in the
system.mhs.
Figure 6: Acknowledge on the IIC Bus
Figure 7: Arbitration of two Masters
1
2
8
9
Clock p
u
l
s
e for
a
cknowledgment
S
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S
TART
condition
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a
cknowledge
Acknowledge
D
a
t
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o
u
tp
u
t
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y tr
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s
mitter
D
a
t
a
o
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tp
u
t
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y receiver
S
CL from
m
as
ter
M
as
ter 1
M
as
ter 2
S
DA
S
CL
S
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