Xantrex Technology XDL 35-5T - Manual (Page 34)

Status Reporting
This section describes the complete status model of the instrument. Note that some registers are
specific to the GPIB section of the instrument and are of limited use in an RS232 environment.
Standard Event Status and Standard Event Status Enable Registers
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Standard Event Status Register which correspond to bits set in the Standard
Event Status Enable Register will cause the ESB bit to be set in the Status Byte Register.
The Standard Event Status Register is read and cleared by the *ESR? command. The Standard
Event Status Enable register is set by the *ESE <nrf> command and read by the *ESE?
command.
Bit 7 - Power On. Set when power is first applied to the instrument.
Bit 6 - Not used.
Bit 5 - Command Error. Set when a syntax type error is detected in a command from the bus.
The parser is reset and parsing continues at the next byte in the input stream.
Bit 4 - Execution Error. Set when an error is encountered while attempting to execute a
completely parsed command. The appropriate error number will be reported in the
Execution Error Register.
1- 99 Indicates a hardware error has been encountered.
116 A recall of set up data has been requested but the store specified does not
contain any data.
117 A recall of set up data has been requested but the store specified contains
corrupted data. This indicates either a hardware fault or a temporary data
corruption which can be corrected by writing data to the store again.
120 The numerical value sent with the command was too big or too small. Includes
negative numbers where only positive numbers are accepted.
123 A recall/store of set up data has been requested from/to an illegal store number.
124 A range change has been requested but the current psu settings make it illegal –
see manual operation instructions for details.
Bit 3 - Verify Timeout Error. Set when a parameter is set with 'verify' specified and the value is
not reached within 5 secs, e.g. output voltage is slowed by a large capacitor on the
output.
Bit 2 - Query Error. Set when a query error occurs. The appropriate error number will be
reported in the Query Error Register as listed below.
1. Interrupted error
2. Deadlock error
3. Unterminated error
Bit 1 - Not used.
Bit 0 - Operation Complete. Set in response to the *OPC command.
Limit Event Status Registers and Limit Event Status Enable Registers
Two pairs of registers are implemented as an addition to the IEEE Std.488.2. Each pair consists of a
Limit Event Status Register and an accompanying Limit Status Event Enable Register. Limit Event
Status Register 1 (LSR1) and Limit Event Status Enable Register 1 (LSE1) apply to output 1. Limit Event
Status Register 2 (LSR2) and Limit Event Status Enable Register 2 (LSE2) apply to output 2 and the
Auxiliary output. Their purpose is to inform the controller of entry to and/or exit from current or voltage
limit conditions by storing a history of protection trip conditions since the last read.
Any bits set in a Limit Event Status Register which correspond to bits set in the accompanying
Limit Event Status Enable Register will cause the LIM1 or LIM2 bit to be set in the Status Byte
Register.
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