Rainbow Electronics MAXQ1004 - Manual (Page 6)

MAXQ1004
1-Wire and SPI Authentication Microcontroller
6
10-BIT ADC PERFORMANCE (continued)
(V DD = 1.7V to 3.6V, V REF = 1.845V, T A = -40NC to +85NC, unless otherwise noted.)
SPI ELECTRICAL CHARACTERISTICS
(V DD = 1.7V to 3.6V, T A = -40NC to +85NC, unless otherwise noted. AC electrical specifications are guaranteed by design and are
not production tested.)
Note 1: Specifications to -40NC are guaranteed by design and are not production tested.
Note 2: The power-fail reset and POR detectors operate in tandem so one or both of these signals are active at all times when
V DD < V RST , ensuring the device maintains the reset state until minimum operating voltage is achieved.
Note 3: The power-fail warning monitor and the power-fail reset monitor track each other with a typical delta between the two of 0.13V.
Note 4: Writes to flash memory must not be performed when the supply voltage drops below the power-fail warning levels, as
there is uncertainty in the duration of continuous power supply. The user application should check the status of the power-
fail warning flag before writing to flash to ensure valid write operations.
Note 5: Measured on the combined AVDD and V DD pins and the part not in reset. All inputs are connected to GND or V DD .
Outputs do not source/sink any current.
Note 6: Guaranteed by design and not production tested.
Note 7: The maximum total current, I
OH(MAX) and I OL(MAX) , for all outputs combined should not exceed 35mA to satisfy the maxi-
mum specified voltage drop.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
10-BIT ADC REFERENCE VOLTAGE
Internal Reference Voltage
V IREF 1.845 Q 5% V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI Master Operating Frequency 1/t
MCK
f
SYSCLK
/2 MHz
SPI Slave Operating Frequency 1/t SCK f SYSCLK /4 MHz
SPI I/O Rise/Fall Time t SPI_RF
C L = 15pF, pullup = 560 W 8.3 23.6 ns
SCLK Output Pulse-Width High/Low t MCH , t MCL t MCK /2 - t SPI_RF ns
MOSI Output Hold Time After SCLK
Sample Edge
t MOH t MCK /2 - t SPI_RF ns
MOSI Output Valid to Sample Edge t MOV t MCK /2 - t SPI_RF ns
MISO Input Valid to SCLK Sample
Edge Rise/Fall Setup
t MIS 25 ns
MISO Input to SCLK Sample Edge
Rise/Fall Hold
t MIH 0 ns
SCLK Inactive to MOSI Inactive t
MLH
t
MCK
/2 - t
SPI_RF
ns
SCLK Input Pulse-Width High/Low t SCH , t SCL t SCK /2 ns
SSEL Active to First Shift Edge t SSE t SPI_RF ns
MOSI Input to SCLK Sample Edge
Rise/Fall Setup
t SIS t SPI_RF ns
MOSI Input from SCLK Sample
Edge Transition Hold
t SIH t SPI_RF ns
MISO Output Valid After SCLK Shift
Edge Transition
t SOV 2t SPI_RF ns
SSEL Inactive t SSH t CK + t SPI_RF ns
SCLK Inactive to SSEL Rising t SD t SPI_RF ns
MISO Output Disabled After SSEL
Edge Rise
t SLH 2t CK + 2t SPI_RF ns