Rainbow Electronics MAXQ2010 - Manual (Page 27)

MAXQ2010
16-Bit Mixed-Signal Microcontroller with LCD
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The watchdog timer is controlled through bits in the
WDCN register. Its timeout period can be set to one of
four programmable intervals ranging from 2
12 to 2 21
system clocks in its default mode, allowing flexibility to
support different types of applications. The interrupt
occurs 512 system clocks before the reset, allowing the
system to execute an interrupt and place the system in
a known, safe state before the device performs a total
system reset. At 8MHz, watchdog timeout periods can
be programmed from 512µs to 67s, depending on the
system clock mode.
Hardware Multiplier
The internal hardware multiplier supports high-speed
multiplications. The multiplier can complete a 16-bit x
16-bit multiply-and-accumulate/subtract operation in a
single cycle with the support of a 48-bit accumulator.
The multiplier is a fixed-point arithmetic unit. The
operands can be either signed or unsigned numbers,
but the data type must be defined by the application
software prior to loading the operand registers.
Seven different multiply operations can be performed
without requiring direct intervention of the microcon-
troller core. These include the following:
• Unsigned 16-bit multiplication
• Unsigned 16-bit multiplication and accumulation
• Unsigned 16-bit multiplication and subtraction
• Signed 16-bit multiplication
• Signed 16-bit multiplication and negate
• Signed 16-bit multiplication and accumulation
• Signed 16-bit multiplication and subtraction
Each of these operations is controlled and accessed
through six SFR registers. The 8-bit multiplier control
register (MCNT) selects the operation, data type,
operand count, optional hardware-based square func-
tion, write option on the MC register, the overflow flag,
and the clear control for operand registers and accu-
mulator. Loading and unloading of the data is achieved
through five 16-bit SFR registers.
Only one cycle is needed for computation. This means
that the result of an operation is ready in the next cycle
immediately following the loading of the last operand.
Back-to-back operations can be performed without wait
states between operations, independent of data type
and operand count.
Analog-to-Digital Converter
The MAXQ2010 contains a 12-bit successive approxi-
mation analog-to-digital converter (ADC) with an analog
mux (Figure 7). The mux selects the ADC input from
eight single-ended channels or four differential chan-
nels. An internal precision bandgap reference can be
used for the ADC reference voltage, or the reference
voltage can be externally driven. Additionally, the ana-
log supply voltage (AV
DD ) can also be used as the volt-
age reference. The ADC runs off a 2.7V to 3.6V power
supply and at a conversion rate up to 300ksps.
The ADC block includes a 12-bit SAR core, ADC con-
trols, a reference generator, and a circular block of six-
teen 12-bit data buffers. The ADC is controlled by SFR
registers. An autoscan feature allows the user to select
up to eight sampling channels for storage in the 16
memory locations.
There are two conversion modes: single-sequence
mode and continuous-sequence mode.
The ADC’s internal power-management system auto-
matically powers down when the conversion(s) are
done (ADCONV = 0). The start conversion bit,
ADCONV, is used to start all conversion processes. If
the ADC power-management override bit is cleared
(ADPMO = 0), the ADC waits for 20 ADCCLK before
starting the first conversion. This allows the ADC time to
set up.
If ADPMO = 1, an ADC conversion is initiated as soon
as ADCONV is set to 1. ADC operation is aborted upon
entry into PMM or stop mode.
The ADCONV bit is set at the beginning of the conver-
sion process and remains set until the conversion
process is finished. In single-sequence mode, this bit
remains set until the ADC has finished conversion on
the last channel in the sequence. In continuous mode,
the ADCONV bit remains set until the continuous mode
is stopped. Writing a 0 to the ADCONV bit stops ADC
operation at the completion of the current ADC conver-
sion. The new data is written to the data buffer.
An A/D conversion takes 16 ADCCLK cycles to com-
plete. Three of the 16 ADCCLK cycles are used for
sample acquisition. The ADCCLK is derived from the
system clock with divide ratio defined by the ADC clock
divider bits (ADCCLK). Therefore, with 16 ADCCLK to
acquire one data, the fastest ADC rate = sysclk/16
(ADCCLK = 0h, ADACQEN = 0h). With a 10MHz sys-
tem clock, this is theoretically equivalent to 10MHz/16
value Msps. Note, however, that the ADC conversion is
limited to 300ksps.
If the ADC data-available interrupt is enabled (ADDAIE
= 1), an interrupt is generated to the CPU when ADDAI
= 1. Once set, the ADADI flag can be cleared by soft-
ware writing a 0 or at the start of a conversion process
when ADCONV is set to 1. The data-available interrupt
flag (ADDAI) can optionally be set by using the ADC