Rainbow Electronics MAX9476 - Manual (Page 6)

MAX9476
Detailed Description
The MAX9476 is a high-performance clock synthesizer
with an 8kHz input reference clock. This device gener-
ates six identical buffered LVTTL clock outputs at
35.328MHz. The internal PLL phase locks the external
crystal (35.328MHz) to the 8kHz input reference clock.
This device features a low-jitter output that provides a
better source for the reference clock relay (see the
Functional Diagram).
Power-Up
At power-up, all the outputs are disabled and pulled low
(to GND) for at least 256ms. After 256ms, the crystal
oscillator starts oscillation. If the reference clock is not
present at power-up, the outputs are forced to the cen-
ter frequency of the crystal oscillator.
Reference CLK Monitor
The MAX9476 features internal clock (CLK) monitor cir-
cuitry to detect the presence of the external 8kHz refer-
ence clock. The internal CLK monitor continuously
monitors the number of low-to-high transitions within a
three-cycle (at 8kHz) time window. If the transition num-
ber is less than two, the internal CLK monitor states loss
of the reference CLK. However, if in a three-cycle time
window the monitor counts two or three transitions, it
considers the input reference clock as present. When
the monitor detects the absence of the 8kHz reference
clock, the outputs are operating at the center frequency
of the crystal oscillator. However, when the monitor
detects the return of the reference clock, the PLL locks
to the reference clock. The ratio between the external
crystal and the input reference clock is 4416.
Clock Outputs (CLK1 to CLK6) and REO
The MAX9476 uses a 35.328MHz crystal and a refer-
ence clock (REIN) to generate six identical outputs,
CLK1 to CLK6, at 35.328MHz. All CLK_ outputs are
LVTTL with a typical skew of 185ps. The MAX9476 also
regenerates the 8kHz reference CLK at REO output.
Voltage-Controlled Crystal
Oscillator (VCXO)
The MAX9476’s internal VCXO takes an external
35.328MHz crystal as the base frequency and has a
pulling range of approximately ±100ppm. This configu-
ration also makes the VCXO PLL become a narrowband
filter to reject high-frequency jitter on the input reference
and eliminate it from the REO and CLK_ outputs.
SHDN
Mode
The MAX9476 features a shutdown mode with a supply
current of 7.5µA (typ). Drive SHDN low to get the
device into shutdown mode. In this mode, all the out-
puts go low and the PLL is powered down. After SHDN
goes high, the outputs still stay low for an additional
256ms to allow the PLL to be stabilized before the out-
puts are enabled again.
Applications Information
Crystal Selection
The MAX9476 uses a 35.328MHz crystal as the base
frequency for the VCXO. It is important to use a correct
type of quartz crystal to avoid reducing frequency
pulling range, or excessive output phase jitter.
Choose an AT-cut crystal that oscillates at 35.328MHz
on its fundamental mode with a variation of ±25ppm
including frequency accuracy and operating tempera-
ture range. The crystal’s load capacitance should be
14pF. Pulling range may vary depending on the crystal
used. Refer to the MAX9476 evaluation kit for details.
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
6 _______________________________________________________________________________________
MAX9476
PLL
CLK2
VCXO
X1
CLK1
V DDP GNDP
/4416
PHASE DETECTOR
AND
CHARGE PUMP
X2
REO
CLK6
CLK5
CLK4
CLK3
GND V DD
LP1 LP2
REFERENCE CLK
MONITOR
REIN
SETI
SHDN
Functional Diagram