Rainbow Electronics MAX7044 - Manual (Page 7)

a 315MHz RF frequency and 4.84ms for a 433MHz RF
frequency. For other frequencies, calculate the wait
time with the following equation:
where t WAIT is the wait time to shutdown and f RF is the
RF transmit frequency.
When the device is in shutdown, a rising edge on DATA
initiates the warm up of the crystal and PLL. The crystal
and PLL must have 220µs settling time before data can
be transmitted. The 220µs turn-on time of the MAX7044
is dominated by the crystal oscillator startup time. Once
the oscillator is running, the 1.6MHz PLL loop band-
width allows fast frequency recovery during power
amplifier toggling.
When the device is operating, each edge on the data
line resets an internal counter to zero and it begins to
count again. If no edges are detected on the data line,
the counter reaches the end-of-count (2
16 clock cycles)
and places the device in shutdown mode. If there is an
edge on the data line before the counter hits the end of
count, the counter is reset and the process starts over.
Phase-Locked Loop
The PLL block contains a phase detector, charge
pump, integrated loop filter, VCO, asynchronous 32x
clock divider, and crystal oscillator. This PLL requires
no external components. The relationship between the
carrier and crystal frequency is given by:
f XTAL = f RF / 32
The lock-detect circuit prevents the power amplifier
from transmitting until the PLL is locked. In addition, the
device shuts down the power amplifier if the reference
frequency is lost.
Power Amplifier
The PA of the MAX7044 is a high-efficiency, open-
drain, class-C amplifier. With a proper output matching
network, the PA can drive a wide range of impedances,
including the small-loop PC board trace antenna and
any 50Ω antenna. The output-matching network for an
antenna with a characteristic impedance of 50Ω is
shown in the
Typical Application Circuit. The output-
matching network suppresses the carrier harmonics
and transforms the antenna impedance to an optimal
impedance at PAOUT, which is about 125Ω.
When the output matching network is properly tuned,
the power amplifier transmits power with high efficiency.
The Typical Application Circuit delivers +13dBm at
+2.7V supply with 7.7mA of supply current. Thus, the
overall efficiency is 48% with the efficiency of the power
amplifier itself greater than 54%.
Buffered Clock Output
The MAX7044 provides a buffered clock output
(CLKOUT) for easy interface to a microcontroller or fre-
quency-hopping generator. The frequency of CLKOUT is
1/16 the crystal frequency. For a 315MHz RF transmit fre-
quency, a crystal of 9.84375MHz is used, giving a clock
output of 615.2kHz. For a 433.92MHz RF frequency, a
crystal of 13.56MHz is used for a clock output of
847.5kHz.
The clock output is inactive when the device is in shut-
down mode. The device is placed in shutdown mode by
the internal data activity detector (see the Shutdown
Mode section). Once data is detected on the data input,
the clock output is stable after approximately 220µs.
Applications Information
Output Power Adjustment
It is possible to adjust the output power down to -15dBm
with the addition of a resistor (see R
PWRADJ in Figure 1).
The addition of the power adjust resistor also reduces
power consumption. See the Supply Current and
Output Power vs. External Resistor and Supply Current
vs. Output Power graphs in the Typical Operating
Characteristics section. It is imperative to add both a
low-frequency and a high-frequency decoupling
capacitor as shown in
Figure 1.
Crystal Oscillator
The crystal oscillator in the MAX7044 is designed to
present a capacitance of approximately 3pF between
the XTAL1 and XTAL2 pins. If a crystal designed to
oscillate with a different load capacitance is used, the
crystal is pulled away from its intended operating fre-
t
x
f
WAIT
RF
=
2 32 16
MAX7044
300MHz to 450MHz High-Efficiency,
Crystal-Based +13dBm ASK Transmitter
_______________________________________________________________________________________ 7
MAX1434
1
XTAL1
ANTENNA
3.0V
3.0V
680pF
R
PWRADJ
220pF
100nF
100nF
XTAL2
f XTAL
8
2
GND V DD
7
3
PAGND DATA INPUT
CLOCK
OUTPUT
(f CLKOUT =
f XTAL /16)
DATA
6
4
PAOUT CLKOUT
5
Figure 1. Output Power Adjustment Circuit