Rainbow Electronics MAX7044 - Manual (Page 8)

MAX7044
quency, thus introducing an error in the reference fre-
quency. Crystals designed to operate with higher differ-
ential load capacitance always pull the reference
frequency higher. For example, a 9.84375MHz crystal
designed to operate with a 10pF load capacitance
oscillates at 9.84688MHz with the MAX7044, causing
the transmitter to be transmitting at 315.1MHz rather
than 315.0MHz, an error of about 100kHz, or 320ppm.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
f p is the amount the crystal frequency is pulled in ppm.
C
m
is the motional capacitance of the crystal.
C case is the case capacitance.
C spec is the specified load capacitance.
C load is the actual load capacitance.
When the crystal is loaded as specified, i.e., C
load
=
C spec , the frequency pulling equals zero.
Output Matching to 50 Ω
When matched to a 50Ω system, the MAX7044 PA is
capable of delivering up to +13dBm of output power at
V
DD = 2.7V. The output of the PA is an open-drain tran-
sistor that requires external impedance matching and
pullup inductance for proper biasing. The pullup induc-
tance from PA to V
DD serves three main purposes: it
resonates the capacitance of the PA output, provides
biasing for the PA, and becomes a high-frequency
choke to reduce the RF energy coupling into V
DD . The
recommended output-matching network topology is
shown in the Typical Application Circuit. The matching
network transforms the 50Ω load to approximately
125Ω at the output of the PA in addition to forming a
bandpass filter that provides attenuation for the higher
order harmonics.
Output Matching to
PC Board Loop Antenna
In some applications, the MAX7044 power amplifier
output has to be impedance matched to a small-loop
antenna. The antenna is usually fabricated out of a cop-
per trace on a PC board in a rectangular, circular, or
square pattern. The antenna will have an impedance
that consists of a lossy component and a radiative
component. To achieve high radiating efficiency, the
radiative component should be as high as possible,
while minimizing the lossy component. In addition, the
loop antenna will have an inherent loop inductance
associated with it (assuming the antenna is terminated
to ground). For example, in a typical application, the
radiative impedance is less than 0.5Ω, the lossy imped-
ance is less than 0.7Ω, and the inductance is approxi-
mately 50nH to 100nH.
The objective of the matching network is to match the
power amplifier output to the small-loop antenna. The
matching components thus transform the low radiative
and resistive parts of the antenna into the much higher
value of the PA output. This gives higher efficiency. The
low radiative and lossy components of the small-loop
antenna result in a higher Q matching network than the
50Ω network; thus, the harmonics are lower.
Layout Considerations
A properly designed PC board is an essential part of
any RF/microwave circuit. At the power amplifier out-
put, use controlled-impedance lines and keep them as
short as possible to minimize losses and radiation. At
high frequencies, trace lengths that are approximately
1/20 the wavelength or longer become antennas. For
example, a 2in trace at 315MHz can act as an antenna.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of PC board trace adds about
20nH of parasitic inductance. The parasitic inductance
can have a dramatic effect on the effective inductance.
For example, a 0.5in trace connecting a 100nH induc-
tor adds an extra 10nH of inductance, or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Using a solid ground plane can reduce the par-
asitic inductance from approximately 20nH/in to 7nH/in.
Also, use low-inductance connections to ground on all
GND pins, and place decoupling capacitors close to all
V
DD connections.
Chip Information
TRANSISTOR COUNT: 2489
PROCESS: CMOS
f
C
Ccase C C C
x
p
m
load case spec
=
+
−
+






2
1 1
10 6
300MHz to 450MHz High-Efficiency,
Crystal-Based +13dBm ASK Transmitter
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