Rainbow Electronics MAX7042 - Manual (Page 11)

MAX7042
308MHz/315MHz/418MHz/433.92MHz
Low-Power, FSK Superheterodyne Receiver
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Mixer
A unique feature of the MAX7042 is the integrated image
rejection of the mixer. This device is designed to elimi-
nate the need for a costly front-end SAW filter in many
applications. The advantages of not using a SAW filter
are increased sensitivity, simplified antenna matching,
less board space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f
LO
= f
RF
- f
IF
). The image-rejection circuit
then combines these signals to achieve a typical image
rejection of approximately 45dB. Low-side injection is
required as high-side injection is not possible due to
the on-chip image rejection. The IF output is driven by
a source follower, biased to create a driving imped-
ance of 330
Ω to interface with an off-chip 330Ω ceram-
ic IF filter. Note that MIXIN+ and MIXIN- are functionally
identical.
Phase-Locked Loop (PLL)
The PLL block contains a phase detector, charge
pump/integrated loop filter, voltage-controlled oscillator
(VCO), asynchronous 32x frequency divider, and crys-
tal oscillator. This PLL does not require any external
components. The relationship between the RF, IF, and
reference frequencies is given by:
To allow the smallest possible IF bandwidth (for best
sensitivity), minimize the tolerance of the reference.
Intermediate Frequency (IF)
The IF section presents a differential 330 Ω load to pro-
vide matching for the off-chip ceramic filter. The inter-
nal six AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB. The limiting ampli-
fiers have a bandpass-filter-type response centered
near the 10.7MHz IF frequency with a 3dB bandwidth
of approximately 10MHz. The limiter output is fed into a
PLL to demodulate the IF, producing a baseband volt-
age with a demodulation slope of 2.1mV/kHz. The RSSI
circuit produces a DC output proportional to the log of
the IF signal level with a slope of approximately
16mV/dB.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and determines the
difference between frequencies as logic ones and
zeros. The PLL is illustrated in Figure 1. The input to the
PLL comes from the output of the IF limiting amplifiers.
The PLL control voltage responds to changes in the fre-
quency of the input signal with a nominal gain of
2.1mV/kHz. For example, an FSK peak-to-peak devia-
tion of 50kHz generates a 105mV
P-P signal on the con-
trol line. This control line is then filtered and sliced by
the FSK baseband circuitry.
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
The maximum calibration time is 120µs, which is includ-
ed in the startup time. Recalibration is necessary after a
significant change in temperature or supply voltage.
Calibration occurs automatically each time the
MAX7042 is powered up. Drive EN low and then high to
force a recalibration.
f
f f
REF
RF IF ( )
=
−
32
LOOP
FILTER
PHASE
DETECTOR
IF
LIMITING
AMPS
TO FSK
BASEBAND FILTER
AND DATA SLICER
10.7MHz VCO
2.1mV/kHz
CHARGE
PUMP
Figure 1. FSK Demodulator PLL Block Diagram