Rainbow Electronics NUC140 - Manual (Page 54)

NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 54 - Revision V1.02
5.18 PDMA Controller
5.18.1 Overview
The NUC1XX contains a peripheral direct memory access (PDMA) controller that transfers data to and
from memory or transfer data to and from APB devices. The PDMA has nine channels of DMA
(Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory). For each PDMA channel
(PDMA CH0~CH8), there is one word buffer as transfer buffer between the Peripherals APB devices
and Memory.
Software can stop the PDMA operation by disable PDMA [PDMACEN]. The CPU can recognize the
completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt.
The NUC1XX PDMA controller can increment source or destination address, fixed or wrap around
them as well.
5.18.2 Features
y AMBA AHB master/slave interface compatible, for data transfer and register read/write.
y PDMA support 32-bit source and destination addressing range address increment, fixed and
wrap around.