Rainbow Electronics MAX6902 - Manual (Page 11)

MAX6902
SPI-Compatible RTC in a TDFN
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Using the On-Board RAM
The static RAM is 31 x 8 bits addressed consecutively
in the RAM Address/Command space. Table 2 details
the specific hex Address/Commands for Reads and
Writes to each of the 31 locations of RAM. The contents
of the RAM are static and remain valid for V
CC down to
2V. All RAM data are lost if power is cycled. The Write-
Protect Bit (bit 7 of the Control register), when high, dis-
allows any writes to RAM.
SPI-Compatible Serial
Interface
Interface the MAX6902 with a microcontroller using a
serial, 4-wire, SPI interface. SPI is a synchronous bus
for address and data transfer, and is used with
Motorola or other microcontrollers that have an SPI
port. Four connections are required for the interface:
DOUT (Serial Data Out); DIN (Serial Data In); SCLK
(Serial Clock); and CS (Chip Select). In an SPI applica-
tion, the MAX6902 acts as a slave device and the
microcontroller acts as the master. CS is asserted low
by the microcontroller to initiate a transfer, and
deasserted high to terminate a transfer. DIN transfers
input data from the microcontroller to the MAX6902.
DOUT transfers output data from the MAX6902 to the
microcontroller. A shift clock, SCLK, is used to synchro-
nize data movement between the microcontroller and
the MAX6902. SCLK, which is generated by the micro-
controller, is active only during address and data trans-
fer to any device on the SPI bus. The inactive clock
polarity is usually programmable on the microcontroller
side of the SPI interface. In the MAX6902, input data
are latched on the positive edge, and output data are
shifted out on the negative edge. There is one clock
cycle for each bit transferred. Address and data bits
are transferred in groups of eight.
The SPI protocol allows for one of four combinations of
serial clock phase and polarity from the microcontroller,
through a 2-bit selection in its SPI Control register. The
clock polarity is specified by the CPOL Control bit,
which selects active-high or active-low clock, and has
no significant effect on the transfer format. The Clock
Phase Control bit, CPHA, selects one of two different
transfer formats. The clock phase and polarity must be
identical for the master and the slave. For the
MAX6902, set the control bits to CPHA = 1 and CPOL =
1. This configures the system for data to be launched
on the negative edge of SCLK and sampled on the
positive edge. With CPHA equal to 1, CS can remain
low between successive data byte transfers, allowing
burst-mode data transfers to occur.
Address and data bytes are shifted MSB first into DIN
of the MAX6902, and out of DOUT. Data are shifted out
at the negative edge of SCLK, and shifted in or sam-
pled at the positive edge of SCLK. Any transfer
requires an Address/Command byte followed by one or
more bytes of data. Data are transferred out of DOUT
for a read operation, and into DIN for a write operation.
DOUT transmits data only after an Address/Command
byte specifies a read operation; otherwise, it is high
impedance.
Data Transfer Write timing is shown in Figure 3. Data
Transfer Read timing is shown in Figure 4. Detailed
Read and Write Timing is shown in Figure 5.
SCLK
0 R* A5 A4 A3 A2 A1 1 D7 D6 D5 D4 D3 D2 D1 D0
DIN
DOUT
ADDRESS/COMMAND BYTE DATA BYTE
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
CS
* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.
Figure 3a. Single Write