Rainbow Electronics MAX9860 - Manual (Page 16)

MAX9860
Status/Interrupt
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon a read operation of
the status register and are set the next time the event
occurs. Register 0x02 determines whether or not the sta-
tus flags in register 0x00 simultaneously sets IRQ high.
16-Bit Mono Audio Voice Codec
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Table 2. Status/Interrupt Registers
REGISTER ADDRESS B7 B6 B5 B4 B3 B2 B1 B0
0x00 CLD SLD ULK 0 0 0 0 0
0x01 NG AGC
0x02 ICLD ISLD IULK 0 0 0 0 0
BITS FUNCTION
CLD
Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC digital signal paths. CLD also
indicates that the AGC function, when enabled, has set the microphone PGA to 0dB and no further gain reduction
is possible.
SLD
Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all
intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value.
ULK
Digital PLL Unlock Flag. Indicates that the digital audio PLL for the ADC or DAC has become unlocked and digital
signal data is not reliable. When beginning operation in master mode, this flag goes high and can be cleared by
reading the status register.
Noise Gate Attenuation. When the noise gate is enabled these bits indicate the current noise gate attenuation.
Code Attenuation
000 0dB
001 1dB
010 2dB
011 3dB
100 6dB
101 8dB
110 10dB
NG
111 12dB
AGC
AGC Gain. When the AGC is enabled these bits indicate the AGC controlled level to the MIC preamp. The levels
indicated by these bits correspond to the levels defined for the PGAM bits described in register 0x0C.