Rainbow Electronics MAX9597 User Manual
Page 17
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
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17
Conditions
section). SDA and SCL idle high when the
I
2
C bus is not busy.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 5). A START
condition from the master signals the beginning of a
transmission to the MAX9597. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9597 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/W bit to 1 to configure the MAX9597 to read mode.
Set the R/W bit to 0 to configure the MAX9597 to write
mode. The slave address is always the first byte of
information sent to the MAX9597 after a START or a
REPEATED START condition. The MAX9597 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the MAX9597.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9597 uses to handshake receipt of each byte of
data when in write mode (see Figure 6). The MAX9597
pulls down SDA during the entire master-generated
ninth clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication. The
master pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9597 is in
read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not
acknowledge is sent when the master reads the final
byte of data from the MAX9597, followed by a STOP
condition.
Write Data Format
A write to the MAX9597 consists of transmitting a
START condition, the slave address with the R/W bit set
to 0, one data byte to configure the internal register
address pointer, one or more data bytes, and a STOP
condition. Figure 7 illustrates the proper frame format
for writing one byte of data to the MAX9597. Figure 8
illustrates the frame format for writing n-bytes of data to
the MAX9597.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9597.
The MAX9597 acknowledges receipt of the address
byte during the master-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9597’s internal register address pointer.
The pointer tells the MAX9597 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9597 upon receipt of the address pointer data.
The third byte sent to the MAX9597 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9597 signals receipt of the data
byte. The address pointer autoincrements to the next
SCL
SDA
S
Sr
P
Figure 5. START, STOP, and REPEATED START Conditions
1
SCL
START
CONDITION
SDA
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 6. Acknowledge