Sub-block reset control register (actl_reset) – Rainbow Electronics W90N745CDG User Manual
Page 242
W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
-
237
-
Revision
A2
Sub-block reset control register (ACTL_RESET)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
ACTL_RESET
0xFFF0_9004 R/W
Sub block reset control
0x0000_0000
The value in ACTL_RESET register control the reset operation in each sub block.
BITS
DESCRIPTIONS
[31:17]
Reserved -
[16]
ACTL_RESET
Audio controller reset control bit
1 = the whole audio controller is reset
0 = the audio controller is normal operation
The ACTL_RESET bit is read/write
[15:14]
RECORD_SINGLE
[1:0]
record single/dual channel select bits
2’b11= the record is dual channel
2’b01= the record only select left channel
2’b10= the record only select right channel
2’b00 is reserved
Note that, when ADC is selected as record path, it only
support left channel record.
The PLAY_SINGLE[1:0] bits are read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ACTL_RESET
15
14
13
12
11
10
9
8
RECORD_SINGLE[1:0] PLAY_SINGLE[1:0]
Reserved
AC_RECOR
D
7
6
5
4
3
2
1
0
AC_PLAY
I
²
S_RECORD I
²
S_PLAY
Reserved AC_RESET
I
²
S_RESET