Rainbow Electronics W90N745CDG - Manual (Page 342)

W90N745CD/W90N745CDG
- 338 -
6.14 I 2 C Interface
I 2 C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I 2 C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up
to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and
400kbps modes are supported directly. For High-speed mode special IOs are needed. If these IOs are
available and used, then High-speed mode is also supported.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-
by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the
MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled
during the high period of SCL; therefore, the SDA line may be changed only during the low period of
SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is
high is interpreted as a command (START or STOP).
The I
2 C Master Core includes the following features:
• AMBA APB interface compatible
• Compatible with Philips I 2 C standard, support master mode
• Multi Master Operation
• Clock stretching and wait state generation
• Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
• Software programmable acknowledge bit
• Arbitration lost interrupt, with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Supports 7 bit addressing mode
• Fully static synchronous design with one clock domain
• Software mode I 2 C